EPF10K20RC240-3 vs EPF10K20RC240-3N Comparación
Comparación detallada lado a lado de EPF10K20RC240-3 por Intel y EPF10K20RC240-3N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPF10K20RC240-3 | EPF10K20RC240-3N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $21,20 | $23,10 |
| Family | FLEX 10K | Embedded Programmable Logic Device (EPLD) |
| Series | FLEX-10K® | FLEX 10K |
| Typical Gates | 20,000 | — |
| Logic Elements (LEs) | 12,288 | — |
| Logic Array Blocks (LABs) | 189 | 144 |
| Flip-Flops | 1,152 | — |
| Embedded Array Blocks (EABs) | 6 (2 Kbit each) | 6 (per family architecture) |
| Total EAB RAM | 12 Kbits | — |
| User I/Os | 470 (max per package) | — |
| Encapsulado | 240-BFQFP Exposed Pad (RQFP-240) | — |
| Process Technology | 0.42 µm CMOS, 5 metal layers | — |
| Core Supply Voltage (VCCINT) | 5 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5 V tolerant | — |
| Propagation Delay (tpd) | 0.4 ns | — |
| Maximum Internal Frequency | 125 MHz | 125 MHz |
| Temperatura de funcionamiento | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (commercial) |
| Speed Grade | -3 | -3 |
| Configuration Interface | JTAG (IEEE 1149.1) + serial configuration PROM | — |
| Tipo de montaje | Surface Mount | Surface Mount (gull wing) |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Estado RoHS | unknown (legacy Altera part, likely non-RoHS) | [DATA_NEEDED: RoHS compliance] |
| Programming | SRAM-based, in-system reconfigurable | — |
| Logic Cells / Elements | — | 1152 |
| Total Gates | — | 20,000 (typical usable) |
| Logic Capacity (typical) | — | 12,888 |
| User I/O Pins | — | 189 |
| Número de pines | — | 240 |
| Package Type | — | 240-RQFP (HFQFP, exposed pad) |
| Package Code | — | HFQFP / RQFP |
| Tensión de alimentación | — | 5 V |
| Technology / Process | — | 0.42 µm CMOS |
| Propagation Delay | — | 0.4 ns (typical) |
| Programming Interface | — | JTAG (IEEE 1149.1), ByteBlaster / MasterBlaster / ByteBlasterMV |
| Configuration Memory | — | SRAM (volatile, re-programmable) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |