EPF10K20RC240-3 vs EPF10K20RC240-3N Comparaison
Comparaison détaillée côte à côte de EPF10K20RC240-3 par Intel et EPF10K20RC240-3N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF10K20RC240-3 | EPF10K20RC240-3N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $21,20 | $23,10 |
| Family | FLEX 10K | Embedded Programmable Logic Device (EPLD) |
| Series | FLEX-10K® | FLEX 10K |
| Typical Gates | 20,000 | — |
| Logic Elements (LEs) | 12,288 | — |
| Logic Array Blocks (LABs) | 189 | 144 |
| Flip-Flops | 1,152 | — |
| Embedded Array Blocks (EABs) | 6 (2 Kbit each) | 6 (per family architecture) |
| Total EAB RAM | 12 Kbits | — |
| User I/Os | 470 (max per package) | — |
| Boîtier | 240-BFQFP Exposed Pad (RQFP-240) | — |
| Process Technology | 0.42 µm CMOS, 5 metal layers | — |
| Core Supply Voltage (VCCINT) | 5 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5 V tolerant | — |
| Propagation Delay (tpd) | 0.4 ns | — |
| Maximum Internal Frequency | 125 MHz | 125 MHz |
| Température de fonctionnement | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (commercial) |
| Speed Grade | -3 | -3 |
| Configuration Interface | JTAG (IEEE 1149.1) + serial configuration PROM | — |
| Type de montage | Surface Mount | Surface Mount (gull wing) |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Statut RoHS | unknown (legacy Altera part, likely non-RoHS) | [DATA_NEEDED: RoHS compliance] |
| Programming | SRAM-based, in-system reconfigurable | — |
| Logic Cells / Elements | — | 1152 |
| Total Gates | — | 20,000 (typical usable) |
| Logic Capacity (typical) | — | 12,888 |
| User I/O Pins | — | 189 |
| Nombre de broches | — | 240 |
| Package Type | — | 240-RQFP (HFQFP, exposed pad) |
| Package Code | — | HFQFP / RQFP |
| Tension d'alimentation | — | 5 V |
| Technology / Process | — | 0.42 µm CMOS |
| Propagation Delay | — | 0.4 ns (typical) |
| Programming Interface | — | JTAG (IEEE 1149.1), ByteBlaster / MasterBlaster / ByteBlasterMV |
| Configuration Memory | — | SRAM (volatile, re-programmable) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |