EPM240F100C5N vs EPM240GT100C3 Comparación
Comparación detallada lado a lado de EPM240F100C5N por Intel y EPM240GT100C3 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM240F100C5N | EPM240GT100C3 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $5,20 | $9,95 |
| Device Family | MAX II | — |
| Logic Elements (LEs) | 240 | — |
| Macrocells | 192 | — |
| User I/O Pins (maximum) | 80 | — |
| Pin-to-Pin Logic Delay (tPD) | 4.7 ns | — |
| Maximum Operating Frequency | [DATA_NEEDED: fmax per datasheet] | — |
| Global Clock Networks | [DATA_NEEDED: count] | — |
| Encapsulado | 100-ball FineLine BGA (FBGA-100) | TQFP-100 (100-TQFP, 16 × 16 mm, 0.5 mm pitch) |
| Rango de temperatura de funcionamiento | 0C to +85C (commercial) | — |
| Supply Voltage Core (VCCINT) | 3.3 V | — |
| I/O Bank Voltage (VCCIO) | 1.5V / 1.8V / 2.5V / 3.3V (MultiVolt) | — |
| Configuration Memory | Non-volatile flash (instant-on) | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Programming Interface | JTAG / ByteBlasterMV | IEEE 1149.1 JTAG (ISP) |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Estado RoHS | Compliant | — |
| Family | — | MAX II |
| Logic Elements (LE) | — | 240 |
| Equivalent Macro Cells | — | 192 |
| Pin-to-Pin Delay (tPD) | — | 4.7 ns |
| Maximum Internal Frequency (fMAX) | — | 304 MHz |
| User I/O Count | — | 80 |
| User Flash Memory (UFM) | — | 8 Kbit |
| Process Technology | — | 0.18 µm 6-layer-metal flash |
| Core Supply Voltage | — | 1.8 V (internal) |
| I/O Bank Voltages (MultiVolt) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Temperatura de funcionamiento | — | 0 °C to 85 °C (commercial, C3 suffix) |
| Nivel MSL | — | 3 (168 hours) |