EPM240GT100I5N vs EPM240T100C5 Comparación
Comparación detallada lado a lado de EPM240GT100I5N por Altera y EPM240T100C5 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM240GT100I5N | EPM240T100C5 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $6,31 | $4,92 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX II | MAX II |
| Logic Elements (LEs) | 240 | — |
| Equivalent Macrocells | 192 | — |
| User I/Os | 80 | — |
| Propagation Delay (tPD) | 4.7 ns | — |
| Internal Performance (fMAX) | 304 MHz | — |
| Embedded Non-Volatile Memory | 8 Kbits user Flash | — |
| Process Technology | 0.18 µm 6-layer-metal Flash CMOS | 0.18 µm, 6-layer metal Flash |
| Supply Voltage - Core (VCCINT) | 1.71 V to 1.89 V (3.3 V tolerant for MAX II G variant) | — |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V MultiVolt I/O | — |
| Programming Interface | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) / ISP |
| Encapsulado | 100-pin TQFP (14x14 mm, 0.5 mm pitch) | 100-pin TQFP (14 mm × 14 mm × 1 mm) |
| Temperatura de funcionamiento | -40 °C to +100 °C (Industrial) | 0C to +85C (Commercial) |
| Lead-Free / RoHS | Yes (suffix N) | — |
| Tipo de montaje | Surface Mount | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 192 |
| Maximum User I/O Pins | — | 80 |
| Logic Elements | — | 240 |
| Non-volatile Memory | — | 8 Kbits (embedded Flash) |
| Pin-to-Pin Logic Delay (tPD1) | — | 4.7 ns |
| Maximum Internal Frequency | — | 201.1 MHz |
| Core Supply Voltage | — | 2.5 V / 3.3 V |
| I/O Voltage Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) |
| I/O Banks | — | 4 |
| Chip-wide Output Enable | — | DEV_OE pin |