EPM240GT100I5N vs EPM240T100C5 Comparison
Detailed side-by-side comparison of EPM240GT100I5N by Altera and EPM240T100C5 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM240GT100I5N
EPM240GT100I5N - 240-LE MAX II CPLD, 4.7ns, 100-TQFP | Intel
EPM240GT100I5N β ActiveAltera
EPM240T100C5
EPM240T100C5 - MAX II CPLD, 192 Macrocells, 100-TQFP | Altera
EPM240T100C5 β ActiveSpecification Comparison
| Parameter | EPM240GT100I5N | EPM240T100C5 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $6.31 | $6.20 |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Family | MAX II | MAX II |
| Logic Elements (LEs) | 240 | β |
| Equivalent Macrocells | 192 | β |
| User I/Os | 80 | β |
| Propagation Delay (tPD) | 4.7 ns | β |
| Internal Performance (fMAX) | 304 MHz | β |
| Embedded Non-Volatile Memory | 8 Kbits user Flash | β |
| Process Technology | 0.18 Β΅m 6-layer-metal Flash CMOS | 0.18 Β΅m, 6-layer metal Flash |
| Supply Voltage - Core (VCCINT) | 1.71 V to 1.89 V (3.3 V tolerant for MAX II G variant) | β |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V MultiVolt I/O | β |
| Programming Interface | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) / ISP |
| Package | 100-pin TQFP (14x14 mm, 0.5 mm pitch) | 100-pin TQFP (14 mm Γ 14 mm Γ 1 mm) |
| Operating Temperature | -40 Β°C to +100 Β°C (Industrial) | 0C to +85C (Commercial) |
| Lead-Free / RoHS | Yes (suffix N) | β |
| Mounting Type | Surface Mount | β |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 192 |
| Maximum User I/O Pins | β | 80 |
| Logic Elements | β | 240 |
| Non-volatile Memory | β | 8 Kbits (embedded Flash) |
| Pin-to-Pin Logic Delay (tPD1) | β | 4.7 ns |
| Maximum Internal Frequency | β | 201.1 MHz |
| Core Supply Voltage | β | 2.5 V / 3.3 V |
| I/O Voltage Support | β | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) |
| I/O Banks | β | 4 |
| Chip-wide Output Enable | β | DEV_OE pin |