EPM240T100C4 vs EPM240T100A5N Comparación
Comparación detallada lado a lado de EPM240T100C4 por Intel y EPM240T100A5N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM240T100C4 | EPM240T100A5N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,20 | $7,05 |
| Series | MAX II | — |
| Programmable Type | In System Programmable | — |
| Number of Macrocells | 192 | — |
| Number of Logic Elements/Blocks | 240 | — |
| Number of User I/O | 80 | — |
| Maximum Propagation Delay (tPD) | 4.7 ns | — |
| Internal Supply Voltage | 2.5 V / 3.3 V | — |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| Process Technology | 0.18 µm CMOS, non-volatile Flash | 0.18 µm |
| User Flash Memory | 8 Kbits (typical) | — |
| Encapsulado / Carcasa | 100-pin TQFP | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0 °C to +85 °C (TJ, commercial) | 0C to +85C (commercial, "A5N" suffix) |
| Programming Interface | JTAG (IEEE 1149.1) - ISP | JTAG (IEEE 1149.1) / ISP |
| Supplier Device Package | 100-TQFP (16 × 16 mm, 0.5 mm pitch) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant (Pb-free) |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Family | — | MAX II |
| Macro Cells | — | 192 |
| Logic Elements (LE) | — | 240 |
| User I/O Count | — | 80 |
| Pin-to-Pin Logic Delay (tPD) | — | 4.7 ns |
| Maximum Internal Frequency | — | 201.1 MHz |
| Tensión de alimentación | — | 2.5 V / 3.3 V |
| I/O Bank Count | — | 4 (multi-voltage) |
| Configuration Memory | — | On-chip Flash (instant-on) |
| Encapsulado | — | 100-pin TQFP (14 x 14 x 1.0 mm) |