EPM240T100C4N vs EPM240GT100C5N Comparación
Comparación detallada lado a lado de EPM240T100C4N por Altera y EPM240GT100C5N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM240T100C4N | EPM240GT100C5N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $6,10 | $9,20 |
| Family | MAX II | MAX II |
| Device | EPM240 | — |
| Macro Cells | 192 | — |
| Logic Elements | 240 | — |
| Propagation Delay (tPD) | 4.7 ns (max) | — |
| Maximum Frequency | 247.5 MHz | — |
| User I/O | 80 | — |
| Supply Voltage - Internal | 2.5 V / 3.3 V | — |
| I/O Voltage (MultiVolt) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Process Technology | 0.18 µm | — |
| Programmable Type | In-System Programmable (Flash) | In-System Programmable (ISP) via JTAG |
| Encapsulado / Carcasa | 100-TQFP | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0 °C to +85 °C (commercial, 'C' suffix) | 0C to +85C (Commercial) |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Estado RoHS | Compliant (lead-free, 'N' suffix) | Compliant |
| Series | — | EPM240 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements (LEs) | — | 240 |
| Macrocells | — | 192 |
| User I/Os | — | 80 |
| Pin-to-Pin Delay (tPD) | — | 4.7 ns |
| User Flash Memory (UFM) | — | 8 Kbits |
| Core Supply Voltage (VCCINT) | — | 2.5 V or 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Encapsulado | — | 100-pin TQFP (T100) |
| Configuration Memory | — | Non-volatile Flash (instant-on) |
| Nivel MSL | — | 3 |