EPM3032ALC44-4N vs EPM3032ALC44-7 Comparación
Comparación detallada lado a lado de EPM3032ALC44-4N por Intel y EPM3032ALC44-7 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3032ALC44-4N | EPM3032ALC44-7 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1,32 | $0,95 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 32 | — |
| Logic Array Blocks (LABs) | 2 | 2 |
| Usable Gates | 600 | — |
| User I/O Pins | 34 | — |
| Pin-to-Pin Delay (tPD) | 4.5 ns | — |
| Maximum Counter Frequency (fCNT) | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Encapsulado | 44-pin PLCC (J-Lead) | 44-pin PLCC (J-Lead), 16.59 x 16.59 mm, 3.81 mm height |
| Tipo de montaje | Surface Mount | Surface Mount |
| Programmability | EEPROM (non-volatile), IEEE 1149.1 JTAG ISP, IEEE 1532 compliant | — |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial/commercial grade] | 0 °C to +70 °C (Commercial) |
| Estado RoHS | [DATA_NEEDED: from datasheet] | Not Compliant (per Arrow listing) |
| Logic Elements / Macrocells | — | 32 macrocells |
| System Gates | — | 600 |
| Number of User I/O Pins | — | 34 |
| Global Clocks | — | 2 |
| Propagation Delay (tPD1, max) | — | 7.5 ns |
| Maximum Internal Frequency (fMAX) | — | 138.9 MHz |
| Supply Voltage (VCCINT / VCCIO) | — | 3.3 V |
| I/O Tolerant Voltage | — | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Program Memory Type | — | EEPROM |
| In-System Programming (ISP) | — | Yes - IEEE 1149.1 JTAG |
| Part Status | — | Obsolete |
| ECCN | — | EAR99 |