EPM3032ALC44-4N vs EPM3032ALC44-7 对比

详细并排对比 EPM3032ALC44-4N 出自 Intel 和 EPM3032ALC44-7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3032ALC44-4N EPM3032ALC44-7
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $1.32 $0.95
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 32 —
Logic Array Blocks (LABs) 2 2
Usable Gates 600 —
User I/O Pins 34 —
Pin-to-Pin Delay (tPD) 4.5 ns —
Maximum Counter Frequency (fCNT) 227.3 MHz —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (MultiVolt) —
封装 44-pin PLCC (J-Lead) 44-pin PLCC (J-Lead), 16.59 x 16.59 mm, 3.81 mm height
安装类型 Surface Mount Surface Mount
Programmability EEPROM (non-volatile), IEEE 1149.1 JTAG ISP, IEEE 1532 compliant —
工作温度 [DATA_NEEDED: industrial/commercial grade] 0 °C to +70 °C (Commercial)
RoHS 状态 [DATA_NEEDED: from datasheet] Not Compliant (per Arrow listing)
Logic Elements / Macrocells — 32 macrocells
System Gates — 600
Number of User I/O Pins — 34
Global Clocks — 2
Propagation Delay (tPD1, max) — 7.5 ns
Maximum Internal Frequency (fMAX) — 138.9 MHz
Supply Voltage (VCCINT / VCCIO) — 3.3 V
I/O Tolerant Voltage — 2.5 V / 3.3 V / 5.0 V (MultiVolt)
Program Memory Type — EEPROM
In-System Programming (ISP) — Yes - IEEE 1149.1 JTAG
Part Status — Obsolete
ECCN — EAR99

数据手册与资源

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