EPM3032ATC44-10NAB vs EPM3032ATC44-10 Comparación
Comparación detallada lado a lado de EPM3032ATC44-10NAB por Intel y EPM3032ATC44-10 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM3032ATC44-10NAB - 32-Macrocell CPLD, 10ns, 3.3V | Intel (Altera)
EPM3032ATC44-10NAB ObsoleteComparación de especificaciones
| Parámetro | EPM3032ATC44-10NAB | EPM3032ATC44-10 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $4,10 | $0,78 |
| Product Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Elements / Macrocells | 32 macrocells | — |
| Usable Gates | 600 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 103.1 MHz (per Arrow listing) | — |
| Number of User I/O | 34 (max for 44-pin TQFP package) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V (MultiVolt I/O compatible with 5.0 V, 3.3 V, 2.5 V logic) | — |
| Encapsulado | 44-pin TQFP | 44-pin TQFP (10x10 mm) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE Std. 1149.1 / IEEE Std. 1532 ISP) | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Hot-Socketing Support | Yes | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0 °C to +70 °C (commercial, 'C' grade) |
| Estado RoHS | Compliant (per -NAB suffix convention) | Compliant |
| Delivery Form | Tray ('AB' suffix per Altera order code convention) | — |
| Process Technology | CMOS, EEPROM-based | — |
| Series | — | MAX 3000A |
| Family | — | CPLD MAX 3000A |
| Number of Macrocells | — | 32 |
| Number of Logic Array Blocks (LABs) | — | 2 |
| Number of Usable Gates | — | 600 |
| Number of I/O Pins | — | 34 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Voltage Tolerance | — | MultiVolt (1.8 V / 2.5 V / 3.3 V / 5.0 V) |
| Technology | — | CMOS EEPROM |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Nivel MSL | — | [DATA_NEEDED: MSL Level] |
| Lead-Free | — | Yes |