EPM3064ALI44-10N vs EPM3064ATC44-10NAF Comparación
Comparación detallada lado a lado de EPM3064ALI44-10N por Altera y EPM3064ATC44-10NAF por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3064ATC44-10NAF - 64-Macrocell MAX 3000A CPLD, 10ns TQFP-44 | Intel
EPM3064ATC44-10NAF NrndComparación de especificaciones
| Parámetro | EPM3064ALI44-10N | EPM3064ATC44-10NAF |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,80 | $5,05 |
| Series | MAX 3000A | MAX 3000A |
| Programmable Type | In System Programmable (ISP) | — |
| Number of Macrocells | 64 | — |
| Number of I/O | 34 | — |
| Logic Gates | 1250 gates | — |
| Number of Logic Elements/Blocks | 4 LABs | — |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | — |
| Counter Frequency | up to 227.3 MHz | — |
| Supply Voltage - Core | 3.3 V | — |
| I/O Logic Level Support | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG | — |
| Temperatura de funcionamiento | -40 C to +85 C (Industrial) | [DATA_NEEDED: industrial/commercial grade] |
| Encapsulado | 44-pin PLCC (J-Lead) | TQFP-44 (10x10 mm) |
| Tipo de montaje | Surface Mount (socketable PLCC) | Surface Mount |
| Lead Free / RoHS Status | Lead Free, RoHS Compliant | — |
| Hot-Socketing Support | Yes | — |
| Configuration Memory | CMOS EEPROM (non-volatile) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 64 |
| Logic Elements / LABs | — | 4 LABs (16 macrocells per LAB) |
| Usable Gates | — | 1250 |
| Number of I/O Pins | — | 34 |
| Propagation Delay (tPD, max) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| I/O Voltage Tolerance | — | Multi-voltage (3.3 V / 2.5 V / 1.8 V capable) |
| Programmable Technology | — | EEPROM (non-volatile) |
| In-System Programmable | — | Yes (IEEE Std. 1532 compliant) |
| Boundary-Scan Test | — | Yes (IEEE Std. 1149.1 JTAG) |
| Pin-Locking | — | Yes |
| Lead Finish | — | Lead-free (NiPdAu, AF suffix) |
| Estado RoHS | — | Compliant |
| Configuration Memory Cycles | — | 100 erase/program cycles |