EPM3064ATC44-10 vs EPM3064ATC44-10NAF Comparación
Comparación detallada lado a lado de EPM3064ATC44-10 por Altera y EPM3064ATC44-10NAF por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3064ATC44-10NAF - 64-Macrocell MAX 3000A CPLD, 10ns TQFP-44 | Intel
EPM3064ATC44-10NAF NrndComparación de especificaciones
| Parámetro | EPM3064ATC44-10 | EPM3064ATC44-10NAF |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $4,35 | $5,05 |
| Family | MAX 3000A | — |
| Logic Elements / Macrocells | 64 macrocells | — |
| Usable Gates | 1,250 | 1250 |
| Number of Logic Blocks / LABs | 4 LABs | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency | 227.3 MHz (counter speed) | — |
| Programmable I/Os | 34 | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | 3.0 V to 3.6 V |
| I/O Bank Voltage (VCCIO) | MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Technology | CMOS EEPROM, 5 V tolerant I/O | — |
| In-System Programming | IEEE Std. 1532 (JTAG) | — |
| Boundary-Scan Support | IEEE 1149.1 (JTAG) | — |
| Encapsulado | TQFP-44, 10 x 10 mm, 0.8 mm pitch | TQFP-44 (10x10 mm) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Rango de temperatura de funcionamiento | 0C to +70C (commercial) | — |
| Estado RoHS | Non-compliant (legacy Altera, Pb-bearing) | Compliant |
| Series | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 64 |
| Logic Elements / LABs | — | 4 LABs (16 macrocells per LAB) |
| Number of I/O Pins | — | 34 |
| Propagation Delay (tPD, max) | — | 10 ns |
| I/O Voltage Tolerance | — | Multi-voltage (3.3 V / 2.5 V / 1.8 V capable) |
| Programmable Technology | — | EEPROM (non-volatile) |
| In-System Programmable | — | Yes (IEEE Std. 1532 compliant) |
| Boundary-Scan Test | — | Yes (IEEE Std. 1149.1 JTAG) |
| Pin-Locking | — | Yes |
| Temperatura de funcionamiento | — | [DATA_NEEDED: industrial/commercial grade] |
| Lead Finish | — | Lead-free (NiPdAu, AF suffix) |
| Configuration Memory Cycles | — | 100 erase/program cycles |