EPM3064ATC44-10 vs EPM3064ATC44-10NAF Comparison

Detailed side-by-side comparison of EPM3064ATC44-10 by Altera and EPM3064ATC44-10NAF by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATC44-10 EPM3064ATC44-10NAF
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Family MAX 3000A —
Logic Elements / Macrocells 64 macrocells —
Usable Gates 1,250 1250
Number of Logic Blocks / LABs 4 LABs —
Propagation Delay (tPD) 10 ns —
Maximum Internal Frequency 227.3 MHz (counter speed) —
Programmable I/Os 34 —
Supply Voltage (VCCINT) 3.0 V to 3.6 V (3.3 V typical) 3.0 V to 3.6 V
I/O Bank Voltage (VCCIO) MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V —
Technology CMOS EEPROM, 5 V tolerant I/O —
In-System Programming IEEE Std. 1532 (JTAG) —
Boundary-Scan Support IEEE 1149.1 (JTAG) —
Package TQFP-44, 10 x 10 mm, 0.8 mm pitch TQFP-44 (10x10 mm)
Mounting Type Surface Mount Surface Mount
Operating Temperature Range 0C to +70C (commercial) —
RoHS Status Non-compliant (legacy Altera, Pb-bearing) Compliant
Series — MAX 3000A
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 64
Logic Elements / LABs — 4 LABs (16 macrocells per LAB)
Number of I/O Pins — 34
Propagation Delay (tPD, max) — 10 ns
I/O Voltage Tolerance — Multi-voltage (3.3 V / 2.5 V / 1.8 V capable)
Programmable Technology — EEPROM (non-volatile)
In-System Programmable — Yes (IEEE Std. 1532 compliant)
Boundary-Scan Test — Yes (IEEE Std. 1149.1 JTAG)
Pin-Locking — Yes
Operating Temperature — [DATA_NEEDED: industrial/commercial grade]
Lead Finish — Lead-free (NiPdAu, AF suffix)
Configuration Memory Cycles — 100 erase/program cycles

Datasheets & Resources

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