EPM3064ATC44-10NAF vs EPM3064ATC44-7N Comparación
Comparación detallada lado a lado de EPM3064ATC44-10NAF por Altera y EPM3064ATC44-7N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3064ATC44-10NAF - 64-Macrocell MAX 3000A CPLD, 10ns TQFP-44 | Intel
EPM3064ATC44-10NAF NrndComparación de especificaciones
| Parámetro | EPM3064ATC44-10NAF | EPM3064ATC44-7N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $5,05 | $2,30 |
| Series | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 64 | 64 |
| Logic Elements / LABs | 4 LABs (16 macrocells per LAB) | — |
| Usable Gates | 1250 | 1,250 |
| Number of I/O Pins | 34 | — |
| Propagation Delay (tPD, max) | 10 ns | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | — |
| I/O Voltage Tolerance | Multi-voltage (3.3 V / 2.5 V / 1.8 V capable) | — |
| Programmable Technology | EEPROM (non-volatile) | — |
| In-System Programmable | Yes (IEEE Std. 1532 compliant) | — |
| Boundary-Scan Test | Yes (IEEE Std. 1149.1 JTAG) | — |
| Pin-Locking | Yes | — |
| Encapsulado | TQFP-44 (10x10 mm) | 44-pin TQFP |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial/commercial grade] | 0°C to +85°C (commercial) |
| Lead Finish | Lead-free (NiPdAu, AF suffix) | — |
| Estado RoHS | Compliant | Compliant |
| Configuration Memory Cycles | 100 erase/program cycles | — |
| Family | — | MAX 3000A |
| Logic Array Blocks | — | 2 |
| User I/O Pins | — | 34 |
| Número de pines | — | 44 |
| Speed Grade | — | -7 (7.5 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum Counter Frequency | — | 192.3 MHz (-7 grade) |
| Supply Voltage (VCC) | — | 3.3 V |
| MultiVolt I/O | — | 1.8 V / 2.5 V / 3.3 V |
| Programmability | — | EEPROM, in-system programmable (ISP) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| ISP Standard | — | IEEE Std. 1532 compliant |
| Boundary-Scan Test (BST) | — | Built-in, JTAG-driven |