EPM3128AFI256-10N vs EPM3256AFC256-10N Comparación
Comparación detallada lado a lado de EPM3128AFI256-10N por Altera y EPM3256AFC256-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3128AFI256-10N | EPM3256AFC256-10N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,75 | $25,95 |
| Family | MAX 3000A | MAX 3000A |
| Logic Density | 2.5K gates | — |
| Macro Cells | 128 | — |
| User I/Os | 98 | — |
| Speed Grade | -10 (10 ns pin-to-pin) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Logic Family | CMOS, EEPROM-based | CMOS |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Compatibility | 5.0 V, 3.3 V, 2.5 V (MultiVolt) | — |
| In-System Programmability | Yes (JTAG / IEEE 1149.1) | — |
| Encapsulado | 256-ball FineLine BGA (FBGA-256) | 256-pin FineLine BGA |
| Temperatura de funcionamiento | -40C to +85C (industrial, per 'I' suffix) | 0 C to 70 C (commercial) |
| Recuento de pines | 256 | — |
| Estado RoHS | Compliant | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| PCI Compliance | PCI Local Bus Spec Rev 2.2 | PCI Local Bus Specification Rev 2.2 (at -10 grade) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 5,000 gates |
| Macrocells | — | 256 |
| Maximum User I/O | — | 161 |
| Pin-to-Pin Logic Delay | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| Core Voltage | — | 3.3 V |
| I/O Logic Level Compatibility | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Programmability | — | EEPROM, in-system programmable (ISP) |
| JTAG Interface | — | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) |