EPM3128ATC100-10N vs EPM3128ATC100-5N Comparación
Comparación detallada lado a lado de EPM3128ATC100-10N por Altera y EPM3128ATC100-5N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
EPM3128ATC100-10N NrndComparación de especificaciones
| Parámetro | EPM3128ATC100-10N | EPM3128ATC100-5N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $5,20 | $8,20 |
| Family | MAX 3000A | — |
| Product Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | — |
| Usable Gates | 2500 | Up to 10,000 |
| Number of I/O | 80 | — |
| Logic Elements / Blocks | 8 LABs (16 macrocells each) | — |
| Propagation Delay (tPD) | 10 ns | 5 ns |
| Maximum Internal Frequency (fMAX) | 98 MHz | — |
| Supply Voltage VCCINT | 3.3 V | — |
| I/O Bank Voltage VCCIO | 3.3 V or 2.5 V (selectable) | — |
| Configuration Memory | CMOS EEPROM (non-volatile, instant-on) | — |
| In-System Programming | IEEE Std. 1532-compliant ISP via JTAG | — |
| Encapsulado | 100-pin TQFP (14 x 14 x 1.0 mm) | TQFP-100 (TC100) |
| Temperatura de funcionamiento | 0 °C to +70 °C (commercial) | 0 C to +70 C (commercial) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | Compliant | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | Yes | — |
| Nivel MSL | 3 (per JEDEC J-STD-020) | — |
| Device Family | — | MAX 3000A |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 (16 macrocells each) |
| User I/Os | — | 80 |
| Maximum Internal Frequency | — | 192.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 2.5 V |
| Programming Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (IEEE Std. 1532) |
| JTAG Boundary Scan | — | Yes (IEEE 1149.1) |