EPM3128ATC100-10N vs EPM3128ATC100-5N 对比

详细并排对比 EPM3128ATC100-10N 出自 Altera 和 EPM3128ATC100-5N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3128ATC100-10N EPM3128ATC100-5N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 有效
库存状态 有库存 有库存
单价(USD) $5.20 $8.20
Family MAX 3000A —
Product Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 128 —
Usable Gates 2500 Up to 10,000
Number of I/O 80 —
Logic Elements / Blocks 8 LABs (16 macrocells each) —
Propagation Delay (tPD) 10 ns 5 ns
Maximum Internal Frequency (fMAX) 98 MHz —
Supply Voltage VCCINT 3.3 V —
I/O Bank Voltage VCCIO 3.3 V or 2.5 V (selectable) —
Configuration Memory CMOS EEPROM (non-volatile, instant-on) —
In-System Programming IEEE Std. 1532-compliant ISP via JTAG —
封装 100-pin TQFP (14 x 14 x 1.0 mm) TQFP-100 (TC100)
工作温度 0 °C to +70 °C (commercial) 0 C to +70 C (commercial)
安装类型 Surface Mount Surface Mount
RoHS 状态 Compliant [DATA_NEEDED: RoHS compliance]
Lead-Free Yes —
MSL 等级 3 (per JEDEC J-STD-020) —
Device Family — MAX 3000A
Macrocells — 128
Logic Array Blocks (LABs) — 8 (16 macrocells each)
User I/Os — 80
Maximum Internal Frequency — 192.3 MHz
Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 2.5 V
Programming Technology — EEPROM (non-volatile)
In-System Programmability — Yes (IEEE Std. 1532)
JTAG Boundary Scan — Yes (IEEE 1149.1)

数据手册与资源

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