EPM3128ATC144-7 vs EPM3128ATC144-7N Comparación
Comparación detallada lado a lado de EPM3128ATC144-7 por Intel y EPM3128ATC144-7N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3128ATC144-7 | EPM3128ATC144-7N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,10 | $9,25 |
| Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | — |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) | — |
| User I/Os | 96 | 96 |
| Encapsulado | TQFP-144 (22x22 mm) | TQFP-144 (20 x 20 mm, 0.5 mm pitch) |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (multiVolt) | — |
| Speed Grade | -7 | — |
| Pin-to-Pin Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency (fCNT) | 129.9 MHz | — |
| Programming Technology | CMOS EEPROM (in-system programmable) | — |
| JTAG Support | IEEE 1149.1 boundary-scan + ISP | — |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | 0 °C to +70 °C (commercial) |
| Tipo de montaje | Surface Mount | Surface Mount (SMD/SMT) |
| Process Technology | CMOS EEPROM | — |
| Series | — | MAX 3000A |
| Architecture | — | EEPROM-based, MAX architecture |
| Number of Macrocells | — | 128 |
| Number of Usable Gates | — | Up to 10,000 |
| Recuento de pines | — | 144 |
| Logic Family | — | CMOS |
| Propagation Delay (tPD) | — | 7.5 ns (pin-to-pin, -7 speed grade) |
| Counter Frequency | — | Up to 227.3 MHz |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| In-System Programmability (ISP) | — | Yes, via JTAG (IEEE 1149.1) |
| PCI Compliance | — | Compatible with PCI Local Bus Specification Rev. 2.2 |
| Estado RoHS | — | Lead-free (-7N suffix indicates Pb-free finish) |