EPM3128ATC144-7 vs EPM3128ATC144-7N Comparison

Detailed side-by-side comparison of EPM3128ATC144-7 by Intel and EPM3128ATC144-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3128ATC144-7 EPM3128ATC144-7N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Active
Unit Price (USD) — $9.25
Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 128 —
Usable Gates 2,500 —
Logic Array Blocks (LABs) 8 (16 macrocells each) —
User I/Os 96 96
Package TQFP-144 (22x22 mm) TQFP-144 (20 x 20 mm, 0.5 mm pitch)
Supply Voltage (VCCINT) 3.3 V —
I/O Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V (multiVolt) —
Speed Grade -7 —
Pin-to-Pin Propagation Delay (tPD) 7.5 ns —
Maximum Internal Frequency (fCNT) 129.9 MHz —
Programming Technology CMOS EEPROM (in-system programmable) —
JTAG Support IEEE 1149.1 boundary-scan + ISP —
Operating Temperature 0C to +70C (Commercial) 0 °C to +70 °C (commercial)
Mounting Type Surface Mount Surface Mount (SMD/SMT)
Process Technology CMOS EEPROM —
Series — MAX 3000A
Architecture — EEPROM-based, MAX architecture
Number of Macrocells — 128
Number of Usable Gates — Up to 10,000
Pin Count — 144
Logic Family — CMOS
Propagation Delay (tPD) — 7.5 ns (pin-to-pin, -7 speed grade)
Counter Frequency — Up to 227.3 MHz
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V (MultiVolt)
In-System Programmability (ISP) — Yes, via JTAG (IEEE 1149.1)
PCI Compliance — Compatible with PCI Local Bus Specification Rev. 2.2
RoHS Status — Lead-free (-7N suffix indicates Pb-free finish)

Datasheets & Resources

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