EPM3128ATI144-10N vs EPM3128ATI144-5N Comparación
Comparación detallada lado a lado de EPM3128ATI144-10N por Intel y EPM3128ATI144-5N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM3128ATI144-10N - 128-Macrocell MAX 3000A CPLD, 10ns | Intel / Altera
EPM3128ATI144-10N NrndComparación de especificaciones
| Parámetro | EPM3128ATI144-10N | EPM3128ATI144-5N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,32 | $10,50 |
| Family | MAX 3000A | MAX 3000A |
| Logic Type | CMOS EEPROM-based CPLD | — |
| Macrocells | 128 | — |
| Typical Gates | 2.5K | — |
| User I/Os | 96 | 96 |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency | 98 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.0 V to 3.6 V (3.3 V nominal) |
| Output Bank Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| Encapsulado | 144-pin TQFP | TQFP-144 (20x20 mm, 0.5 mm pitch) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | Industrial -40C to +85C | -40C to +85C (industrial) |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) | — |
| JTAG / Boundary Scan | Yes (IEEE 1149.1) | — |
| Configuration Memory | Non-volatile EEPROM | Non-volatile on-chip EEPROM |
| Estado RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Logic Gates | — | 2,500 gates |
| Macro Cells | — | 128 |
| Maximum Operating Frequency | — | 192.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 5.0 ns |
| I/O Standard | — | LVCMOS / LVTTL (5.0 V tolerant inputs) |
| Programming Interface | — | JTAG (IEEE 1149.1 BST) - in-system |
| Process Technology | — | 0.30 um CMOS EEPROM |
| Nivel MSL | — | 3 (168 hours) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |