EPM3128ATI144-7N vs EPM3128ATI144-10N Comparación
Comparación detallada lado a lado de EPM3128ATI144-7N por Altera y EPM3128ATI144-10N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3128ATI144-7N - 128 Macrocell CPLD, 129.9MHz, 3.3V | Altera MAX 3000A
EPM3128ATI144-7N ⚠ Última compraIntel
EPM3128ATI144-10N - 128-Macrocell MAX 3000A CPLD, 10ns | Intel / Altera
EPM3128ATI144-10N NrndComparación de especificaciones
| Parámetro | EPM3128ATI144-7N | EPM3128ATI144-10N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $10,32 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Capacity | 2.5K gates | — |
| Macrocells | 128 | 128 |
| Maximum Frequency (fMAX) | 129.9 MHz | — |
| Pin-to-Pin Propagation Delay | 7.5 ns (speed grade -7) | — |
| User I/O Pins | 96 | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V / 2.5 V / 1.8 V | — |
| Programmable Logic Technology | CMOS EEPROM | — |
| Programming Interface | JTAG (IEEE Std 1149.1) in-system programmable | — |
| Encapsulado | 144-pin TQFP | 144-pin TQFP |
| Terminal Pitch | 0.5 mm | — |
| JEDEC Package Code | S-PQFP-G144 | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | Industrial -40C to +85C |
| MultiVolt I/O | Yes (interfaces with 5.0V/3.3V/2.5V/1.8V logic) | — |
| Logic Type | — | CMOS EEPROM-based CPLD |
| Typical Gates | — | 2.5K |
| User I/Os | — | 96 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 98 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Output Bank Voltage (VCCIO) | — | 3.3 V or 2.5 V |
| Tipo de montaje | — | Surface Mount |
| In-System Programmability | — | Yes (IEEE Std. 1532 compliant) |
| JTAG / Boundary Scan | — | Yes (IEEE 1149.1) |
| Configuration Memory | — | Non-volatile EEPROM |
| Estado RoHS | — | Compliant |