EPM3256ATC144-10N vs EPM7256AETC144-10N Comparación
Comparación detallada lado a lado de EPM3256ATC144-10N por Altera y EPM7256AETC144-10N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Última compraIntel
EPM7256AETC144-10N - MAX 7000A 256-Macro CPLD, 10ns TQFP-144 | Intel
EPM7256AETC144-10N ObsoleteComparación de especificaciones
| Parámetro | EPM3256ATC144-10N | EPM7256AETC144-10N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $14,50 | $15,95 |
| Series | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 | 256 |
| Usable Gates | 5,000 (up to 10,000 usable in family) | 5,000 |
| Number of I/Os | 116 | — |
| Number of Logic Elements / Blocks | 16 LABs | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Global Clocks | 3 | — |
| Global Clear / OE | Yes (1 global clear, 1 global OE) | — |
| Program Memory Type | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Support | IEEE Std. 1149.1 with pin-locking | — |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| Encapsulado | 144-LQFP (TQFP, ATC suffix) | TQFP-144 (ETC suffix) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] | -40C to +85C (industrial) |
| Estado RoHS | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] | [DATA_NEEDED: RoHS status] |
| Lead-Free / Halogen-Free | [DATA_NEEDED: not explicitly confirmed in verified data] | — |
| Family | — | MAX 7000A |
| Logic Array Blocks | — | 16 |
| Maximum User I/O Pins | — | 120 (in 144-pin TQFP) |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 95.2 MHz |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5 V-tolerant |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| Programming Interface | — | IEEE 1149.1 JTAG (ISP) |
| Technology | — | CMOS, EEPROM-based |
| Pin Compatibility | — | Pin-compatible with 5.0V MAX 7000S family |