EPM3256ATC144-10N vs EPM7256AETC144-10N Comparaison
Comparaison détaillée côte à côte de EPM3256ATC144-10N par Altera et EPM7256AETC144-10N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Dernier achatIntel
EPM7256AETC144-10N - MAX 7000A 256-Macro CPLD, 10ns TQFP-144 | Intel
EPM7256AETC144-10N ObsoleteComparaison des spécifications
| Paramètre | EPM3256ATC144-10N | EPM7256AETC144-10N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $14,50 | $15,95 |
| Series | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 | 256 |
| Usable Gates | 5,000 (up to 10,000 usable in family) | 5,000 |
| Number of I/Os | 116 | — |
| Number of Logic Elements / Blocks | 16 LABs | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Global Clocks | 3 | — |
| Global Clear / OE | Yes (1 global clear, 1 global OE) | — |
| Program Memory Type | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Support | IEEE Std. 1149.1 with pin-locking | — |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| Boîtier | 144-LQFP (TQFP, ATC suffix) | TQFP-144 (ETC suffix) |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] | -40C to +85C (industrial) |
| Statut RoHS | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] | [DATA_NEEDED: RoHS status] |
| Lead-Free / Halogen-Free | [DATA_NEEDED: not explicitly confirmed in verified data] | — |
| Family | — | MAX 7000A |
| Logic Array Blocks | — | 16 |
| Maximum User I/O Pins | — | 120 (in 144-pin TQFP) |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 95.2 MHz |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5 V-tolerant |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| Programming Interface | — | IEEE 1149.1 JTAG (ISP) |
| Technology | — | CMOS, EEPROM-based |
| Pin Compatibility | — | Pin-compatible with 5.0V MAX 7000S family |