EPM3256ATC144-7N vs EPM3256ATC144-7 Comparación
Comparación detallada lado a lado de EPM3256ATC144-7N por Altera y EPM3256ATC144-7 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3256ATC144-7N | EPM3256ATC144-7 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,20 | $17,06 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macro Cells | 256 | — |
| Logic Gates (usable) | 5,000 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| User I/Os | 116 | 116 |
| Propagation Delay (tPD) | 7.5 ns | 7.5 ns |
| Maximum Internal Frequency | 126.6 MHz | — |
| Supply Voltage (VCCIO) | 3.0 V to 3.6 V | — |
| Programmable Logic Technology | CMOS EEPROM-based | — |
| In-System Programmable (ISP) | Yes (3.3 V) | — |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Encapsulado | 144-pin TQFP | TQFP-144 (LFQFP, gull-wing) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Logic Family | CMOS | — |
| JTAG Support | IEEE 1149.1 boundary-scan | IEEE Std. 1149.1 boundary-scan |
| Estado RoHS | Compliant | — |
| Macrocells | — | 256 |
| Logic Elements / Gates | — | 600 to 10,000 usable gates |
| Counter Frequency (fCNT) | — | 227.3 MHz |
| Speed Grade | — | -7 |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| Supply Voltage - I/O (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V |
| In-System Programming | — | IEEE Std. 1532 compliant, 3.3 V ISP |
| Recuento de pines | — | 144 |
| PCI Compliance | — | PCI Local Bus Specification Revision 2.2 (speed grades -4 to -10) |