EPM3256ATC144-7N vs EPM3256ATC144-7 对比

详细并排对比 EPM3256ATC144-7N 出自 Altera 和 EPM3256ATC144-7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3256ATC144-7N EPM3256ATC144-7N - MAX 3000A CPLD 256 Macro 7.5ns | Altera

EPM3256ATC144-7N - MAX 3000A CPLD 256 Macro 7.5ns | Altera

EPM3256ATC144-7N ⚠ 最后一次采购

规格对比

参数 EPM3256ATC144-7N EPM3256ATC144-7
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $17.20 $17.06
Family MAX 3000A MAX 3000A
Device Type CPLD - Complex Programmable Logic Device —
Macro Cells 256 —
Logic Gates (usable) 5,000 —
Number of Logic Array Blocks (LABs) 16 —
User I/Os 116 116
Propagation Delay (tPD) 7.5 ns 7.5 ns
Maximum Internal Frequency 126.6 MHz —
Supply Voltage (VCCIO) 3.0 V to 3.6 V —
Programmable Logic Technology CMOS EEPROM-based —
In-System Programmable (ISP) Yes (3.3 V) —
工作温度 0C to +70C (Commercial) 0C to +70C (Commercial)
封装 144-pin TQFP TQFP-144 (LFQFP, gull-wing)
安装类型 Surface Mount Surface Mount
Logic Family CMOS —
JTAG Support IEEE 1149.1 boundary-scan IEEE Std. 1149.1 boundary-scan
RoHS 状态 Compliant —
Macrocells — 256
Logic Elements / Gates — 600 to 10,000 usable gates
Counter Frequency (fCNT) — 227.3 MHz
Speed Grade — -7
Supply Voltage - Core (VCCINT) — 3.3 V
Supply Voltage - I/O (VCCIO) — 2.5 V / 3.3 V / 5.0 V
In-System Programming — IEEE Std. 1532 compliant, 3.3 V ISP
引脚数量 — 144
PCI Compliance — PCI Local Bus Specification Revision 2.2 (speed grades -4 to -10)

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