EPM3256ATC144-7N vs EPM3512ATC144 Comparación
Comparación detallada lado a lado de EPM3256ATC144-7N por Altera y EPM3512ATC144 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3256ATC144-7N | EPM3512ATC144 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,20 | $8,75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macro Cells | 256 | — |
| Logic Gates (usable) | 5,000 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| User I/Os | 116 | — |
| Propagation Delay (tPD) | 7.5 ns | [DATA_NEEDED: tPD in ns] |
| Maximum Internal Frequency | 126.6 MHz | — |
| Supply Voltage (VCCIO) | 3.0 V to 3.6 V | — |
| Programmable Logic Technology | CMOS EEPROM-based | — |
| In-System Programmable (ISP) | Yes (3.3 V) | — |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Encapsulado | 144-pin TQFP | TQFP-144 (20x20 mm) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Logic Family | CMOS | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Estado RoHS | Compliant | Compliant (lead-free suffix variants available) |
| Macrocells | — | 512 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 212 |
| Core Supply Voltage | — | 3.3 V |
| Programming Technology | — | EEPROM (in-system programmable) |
| JTAG Interface | — | IEEE Std. 1149.1 (4-pin) |
| Maximum Frequency | — | 116 MHz |
| Product Terms per Macrocell | — | 32 (expandable) |
| I/O Standards | — | LVTTL, LVCMOS, 2.5 V/3.3 V/5 V tolerant |
| Nivel MSL | — | 3 |