EPM3256ATI144-10N vs EPM3256ATC144-10N Comparación
Comparación detallada lado a lado de EPM3256ATI144-10N por Altera y EPM3256ATC144-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Última compraComparación de especificaciones
| Parámetro | EPM3256ATI144-10N | EPM3256ATC144-10N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,25 | $14,50 |
| Family | MAX 3000A | — |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 256 | — |
| Usable Gates | 5,000 | 5,000 (up to 10,000 usable in family) |
| User I/Os | 116 | — |
| Logic Blocks / Logic Elements | 16 | — |
| Propagation Delay (tPD) | 10 ns | 10 ns |
| Max Frequency (fMAX) | 95.2 MHz | — |
| Supply Voltage - Core | 3.3 V | — |
| I/O Voltage Support | 1.8 V / 2.5 V / 3.3 V (multi-voltage) | — |
| In-System Programmability | Yes, IEEE Std. 1532 compliant | — |
| Boundary-Scan Test (BST) | Yes, IEEE Std. 1149.1 (JTAG) | Built-in, IEEE 1149.1 compliant |
| Encapsulado | 144-pin TQFP | 144-LQFP (TQFP, ATC suffix) |
| Temperatura de funcionamiento | -40 C to +85 C (industrial, "I" suffix) | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] |
| Lead-Free / Pb-Free | Yes ("N" suffix) | — |
| Estado RoHS | Compliant | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] |
| Process Technology | CMOS EEPROM-based, non-volatile | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | 3 (per JEDEC J-STD-020, typical for TQFP) | — |
| Series | — | MAX 3000A |
| Macro Cells | — | 256 |
| Number of I/Os | — | 116 |
| Number of Logic Elements / Blocks | — | 16 LABs |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Maximum Counter Frequency | — | 227.3 MHz |
| Global Clocks | — | 3 |
| Global Clear / OE | — | Yes (1 global clear, 1 global OE) |
| Program Memory Type | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Support | — | IEEE Std. 1149.1 with pin-locking |
| ISP Compliance | — | IEEE Std. 1532 |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: not explicitly confirmed in verified data] |