EPM3256ATI144-10N vs EPM3256ATC144-10N Comparaison
Comparaison détaillée côte à côte de EPM3256ATI144-10N par Altera et EPM3256ATC144-10N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Dernier achatComparaison des spécifications
| Paramètre | EPM3256ATI144-10N | EPM3256ATC144-10N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $10,25 | $14,50 |
| Family | MAX 3000A | — |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 256 | — |
| Usable Gates | 5,000 | 5,000 (up to 10,000 usable in family) |
| User I/Os | 116 | — |
| Logic Blocks / Logic Elements | 16 | — |
| Propagation Delay (tPD) | 10 ns | 10 ns |
| Max Frequency (fMAX) | 95.2 MHz | — |
| Supply Voltage - Core | 3.3 V | — |
| I/O Voltage Support | 1.8 V / 2.5 V / 3.3 V (multi-voltage) | — |
| In-System Programmability | Yes, IEEE Std. 1532 compliant | — |
| Boundary-Scan Test (BST) | Yes, IEEE Std. 1149.1 (JTAG) | Built-in, IEEE 1149.1 compliant |
| Boîtier | 144-pin TQFP | 144-LQFP (TQFP, ATC suffix) |
| Température de fonctionnement | -40 C to +85 C (industrial, "I" suffix) | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] |
| Lead-Free / Pb-Free | Yes ("N" suffix) | — |
| Statut RoHS | Compliant | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] |
| Process Technology | CMOS EEPROM-based, non-volatile | — |
| Type de montage | Surface Mount | Surface Mount |
| Niveau MSL | 3 (per JEDEC J-STD-020, typical for TQFP) | — |
| Series | — | MAX 3000A |
| Macro Cells | — | 256 |
| Number of I/Os | — | 116 |
| Number of Logic Elements / Blocks | — | 16 LABs |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Maximum Counter Frequency | — | 227.3 MHz |
| Global Clocks | — | 3 |
| Global Clear / OE | — | Yes (1 global clear, 1 global OE) |
| Program Memory Type | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Support | — | IEEE Std. 1149.1 with pin-locking |
| ISP Compliance | — | IEEE Std. 1532 |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: not explicitly confirmed in verified data] |