EPM3512AFC256-10N vs EPM3512AFC256-2N Comparación
Comparación detallada lado a lado de EPM3512AFC256-10N por Altera y EPM3512AFC256-2N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM3512AFC256-10N | EPM3512AFC256-2N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $43,22 | $25,80 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Usable Gates | 10000 | — |
| User I/O Pins | 208 | — |
| Logic Array Blocks (LABs) | [DATA_NEEDED: number of LABs] | 32 |
| Operating Frequency (fMAX) | [DATA_NEEDED: fMAX MHz] | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Setup Time (tSU) | 4.5 ns | — |
| VCCINT (Core Supply) | 3.3 V | 3.3 V |
| VCCIO (I/O Supply) | 3.3 V or 2.5 V | 2.5 V / 3.3 V / 5.0 V MultiVolt |
| Technology | CMOS EEPROM-based, non-volatile | — |
| Operating Temperature (Commercial) | 0 C to +70 C | 0 °C to +70 °C |
| Encapsulado | 256-ball FBGA (17 mm x 17 mm) | 256-ball FineLine BGA (FC-256) |
| ISP Interface | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 | — |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount (BGA) |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Maximum User I/O Pins | — | 212 |
| Propagation Delay (tPD) | — | [DATA_NEEDED: tPD in ns] |
| Maximum Operating Frequency | — | [DATA_NEEDED: fMAX in MHz] |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| Configuration Memory | — | Non-volatile EEPROM |
| In-System Programmability | — | IEEE Std. 1532 JTAG |
| PCI Compliance | — | 3.3 V PCI-compliant |
| Lead-Free | — | Yes |