EPM3512AFC256-10N vs EPM3512AFC256-2N 对比

详细并排对比 EPM3512AFC256-10N 出自 Altera 和 EPM3512AFC256-2N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AFC256-10N EPM3512AFC256-2N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $43.22 $25.80
Family MAX 3000A MAX 3000A
Macrocells 512 512
Usable Gates 10000 —
User I/O Pins 208 —
Logic Array Blocks (LABs) [DATA_NEEDED: number of LABs] 32
Operating Frequency (fMAX) [DATA_NEEDED: fMAX MHz] —
Pin-to-Pin Delay (tPD) 10 ns —
Setup Time (tSU) 4.5 ns —
VCCINT (Core Supply) 3.3 V 3.3 V
VCCIO (I/O Supply) 3.3 V or 2.5 V 2.5 V / 3.3 V / 5.0 V MultiVolt
Technology CMOS EEPROM-based, non-volatile —
Operating Temperature (Commercial) 0 C to +70 C 0 °C to +70 °C
封装 256-ball FBGA (17 mm x 17 mm) 256-ball FineLine BGA (FC-256)
ISP Interface IEEE Std. 1149.1 JTAG, IEEE Std. 1532 —
安装类型 Surface Mount (BGA) Surface Mount (BGA)
MSL 等级 [DATA_NEEDED: MSL rating] —
RoHS 状态 [DATA_NEEDED: RoHS status] Compliant
Maximum User I/O Pins — 212
Propagation Delay (tPD) — [DATA_NEEDED: tPD in ns]
Maximum Operating Frequency — [DATA_NEEDED: fMAX in MHz]
Process Technology — 0.30 µm CMOS EEPROM
Configuration Memory — Non-volatile EEPROM
In-System Programmability — IEEE Std. 1532 JTAG
PCI Compliance — 3.3 V PCI-compliant
Lead-Free — Yes

数据手册与资源

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