EPM3512AFC256-20 vs EPM3512AFC256-19 Comparación
Comparación detallada lado a lado de EPM3512AFC256-20 por Altera y EPM3512AFC256-19 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3512AFC256-20 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-20 Obsolete
Comparación de especificaciones
| Parámetro | EPM3512AFC256-20 | EPM3512AFC256-19 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,75 | $10,85 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Typical Usable Gates | 10,000 | — |
| Speed Grade | -20 (20 ns tPD) | -19 |
| Encapsulado | 256-ball FBGA (Fine-pitch BGA) | 256-ball FineLine BGA (FC) |
| Recuento de pines | 256 | — |
| Operating Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Voltage (VCCIO) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| I/O Standards | LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant | — |
| Program Memory Type | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| JTAG Support | Yes (boundary-scan + ISP) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Nivel MSL | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Configuration Memory | Internal EEPROM | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 10000 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum Operating Frequency | — | 80 MHz |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| User I/O Pins | — | 208 |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Supply Voltage VCCIO | — | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP (IEEE 1532) |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| Non-volatile Configuration | — | Yes (EEPROM-based) |