EPM3512AQC208-15N vs EPM3512AQC208-7 Comparación
Comparación detallada lado a lado de EPM3512AQC208-15N por Altera y EPM3512AQC208-7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3512AQC208-15N - 512-Macro CPLD MAX 3000A PQFP-208 | Altera
EPM3512AQC208-15N ⚠ Última compraIntel
EPM3512AQC208-7 - MAX 3000A CPLD, 512 Macrocells, 7.5ns, 208-PQFP | Intel
EPM3512AQC208-7 NrndComparación de especificaciones
| Parámetro | EPM3512AQC208-15N | EPM3512AQC208-7 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $20,50 | $41,72 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 512 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 172 | — |
| Typical Usable Gates | 12,000 | — |
| Number of Logic Elements | 512 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Operating Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt) | — |
| Programmable I/O Standards | LVTTL, LVCMOS, PCI (with external resistor) | — |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| JTAG Support | Yes (BST/Boundary-Scan Test) | — |
| Encapsulado | PQFP-208 (QC208) | 208-Pin PQFP (FQFP, gull-wing) |
| Tipo de montaje | Surface Mount | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0 C to +70 C (commercial) |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Macrocells | — | 512 |
| Usable Gates | — | 10,000 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Counter Frequency (fCNT) | — | 116.3 MHz |
| User I/Os | — | 172 |
| Logic Elements / LEs | — | N/A (CPLD macrocell architecture) |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Standards Supported | — | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) |
| Programming | — | In-System Programmable via JTAG (IEEE Std. 1532) |
| Process Technology | — | CMOS EEPROM, 0.30 um |
| Lead-Free | — | Yes |