EPM3512AQI208-10 vs EPM3512AQC208-10S Comparación
Comparación detallada lado a lado de EPM3512AQI208-10 por Intel y EPM3512AQC208-10S por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM3512AQI208-10 - 512-Macrocell MAX 3000A CPLD, 208-Pin PQFP | Intel
EPM3512AQI208-10 Obsolete
Comparación de especificaciones
| Parámetro | EPM3512AQI208-10 | EPM3512AQC208-10S |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $15,20 | $9,75 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 32 (16 macrocells each) |
| Maximum User I/Os | 172 | — |
| Recuento de pines | 208 | — |
| Package Type | PQFP-208 (FINE LINE BGA-256, FQFP, Gull Wing) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Counter Frequency | 116 MHz | — |
| Logic Family | CMOS, EEPROM-based | CMOS |
| Core Supply Voltage | 3.3 V | — |
| I/O Interface Voltages | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | Yes (PCI Local Bus Specification Rev 2.2) |
| Temperatura de funcionamiento | -40C to +85C (Industrial, I suffix) | 0C to +70C (commercial) |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs_status] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 1750 |
| Encapsulado | — | 208-pin FineLine BGA-256 |
| User I/Os | — | 208 |
| Speed Grade | — | -10 (tPD1 = 7.5 ns) |
| Propagation Delay (tPD1) | — | 7.5 ns (pin-to-pin) |
| Supply Voltage - VCCINT (internal) | — | 3.3 V |
| Supply Voltage - VCCIO (I/O) | — | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) |
| Programming Technology | — | CMOS EEPROM |
| In-System Programmability (ISP) | — | Yes (IEEE Std. 1149.1 JTAG) |
| Boundary-Scan (JTAG) | — | Yes (1149.1 compliant) |
| Program/Erase Endurance | — | 100 cycles minimum |
| Process Technology | — | EEPROM-based CMOS |