EPM3512AQI208-10 vs EPM3512AQC208-10S Comparaison
Comparaison détaillée côte à côte de EPM3512AQI208-10 par Intel et EPM3512AQC208-10S par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPM3512AQI208-10 - 512-Macrocell MAX 3000A CPLD, 208-Pin PQFP | Intel
EPM3512AQI208-10 Obsolete
Comparaison des spécifications
| Paramètre | EPM3512AQI208-10 | EPM3512AQC208-10S |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $15,20 | $9,75 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 32 (16 macrocells each) |
| Maximum User I/Os | 172 | — |
| Nombre de broches | 208 | — |
| Package Type | PQFP-208 (FINE LINE BGA-256, FQFP, Gull Wing) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Counter Frequency | 116 MHz | — |
| Logic Family | CMOS, EEPROM-based | CMOS |
| Core Supply Voltage | 3.3 V | — |
| I/O Interface Voltages | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | Yes (PCI Local Bus Specification Rev 2.2) |
| Température de fonctionnement | -40C to +85C (Industrial, I suffix) | 0C to +70C (commercial) |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs_status] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 1750 |
| Boîtier | — | 208-pin FineLine BGA-256 |
| User I/Os | — | 208 |
| Speed Grade | — | -10 (tPD1 = 7.5 ns) |
| Propagation Delay (tPD1) | — | 7.5 ns (pin-to-pin) |
| Supply Voltage - VCCINT (internal) | — | 3.3 V |
| Supply Voltage - VCCIO (I/O) | — | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) |
| Programming Technology | — | CMOS EEPROM |
| In-System Programmability (ISP) | — | Yes (IEEE Std. 1149.1 JTAG) |
| Boundary-Scan (JTAG) | — | Yes (1149.1 compliant) |
| Program/Erase Endurance | — | 100 cycles minimum |
| Process Technology | — | EEPROM-based CMOS |