EPM3512ATC256-10N vs EPM3512AFI256-10N Comparación
Comparación detallada lado a lado de EPM3512ATC256-10N por Altera y EPM3512AFI256-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera
EPM3512AFI256-10N ⚠ Última compraComparación de especificaciones
| Parámetro | EPM3512ATC256-10N | EPM3512AFI256-10N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $20,10 | $21,75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 208 | — |
| Encapsulado | FBGA-256 (FineLine BGA, 17x17 mm, 1.0 mm pitch) | 256-ball FineLine BGA (FBGA-256) |
| Propagation Delay (tPD1) | 10 ns | — |
| Core Supply Voltage (VCCINT) | 3.3 V | 3.3 V (3.0 V to 3.6 V) |
| I/O Supply Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| Programming Interface | JTAG (IEEE Std. 1149.1) - in-system programmable | — |
| Temperatura de funcionamiento | 0 C to +70 C (commercial, "C" suffix) | — |
| Process Technology | 0.30 um CMOS EEPROM | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | unknown | Compliant |
| Lead-Free | unknown | — |
| Series | — | EPM3512 |
| Architecture | — | CMOS EEPROM-based, MAX architecture |
| Number of Macrocells | — | 512 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| Usable Gates | — | Up to 10,000 |
| Number of User I/O | — | 208 |
| Total Pins | — | 256 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| MultiVolt I/O Support | — | 5.0 V / 3.3 V / 2.5 V |
| In-System Programmability | — | Yes - IEEE Std 1532 compliant |
| JTAG Boundary Scan | — | Yes - IEEE 1149.1 |
| Program Memory | — | EEPROM (non-volatile) |
| Rango de temperatura de funcionamiento | — | -40 °C to +85 °C (industrial) |
| Speed Grade | — | -10 (10 ns tPD) |