EPM3512ATC256-10N vs EPM3512AFI256-10N 비교
다음의 상세 나란히 비교: EPM3512ATC256-10N 제조: Altera 및 EPM3512AFI256-10N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera
EPM3512AFI256-10N ⚠ 최종 구매사양 비교
| 파라미터 | EPM3512ATC256-10N | EPM3512AFI256-10N |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $20.10 | $21.75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 208 | — |
| 패키지 | FBGA-256 (FineLine BGA, 17x17 mm, 1.0 mm pitch) | 256-ball FineLine BGA (FBGA-256) |
| Propagation Delay (tPD1) | 10 ns | — |
| Core Supply Voltage (VCCINT) | 3.3 V | 3.3 V (3.0 V to 3.6 V) |
| I/O Supply Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| Programming Interface | JTAG (IEEE Std. 1149.1) - in-system programmable | — |
| 동작 온도 | 0 C to +70 C (commercial, "C" suffix) | — |
| Process Technology | 0.30 um CMOS EEPROM | — |
| 실장 유형 | Surface Mount | Surface Mount |
| RoHS 상태 | unknown | Compliant |
| Lead-Free | unknown | — |
| Series | — | EPM3512 |
| Architecture | — | CMOS EEPROM-based, MAX architecture |
| Number of Macrocells | — | 512 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| Usable Gates | — | Up to 10,000 |
| Number of User I/O | — | 208 |
| Total Pins | — | 256 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| MultiVolt I/O Support | — | 5.0 V / 3.3 V / 2.5 V |
| In-System Programmability | — | Yes - IEEE Std 1532 compliant |
| JTAG Boundary Scan | — | Yes - IEEE 1149.1 |
| Program Memory | — | EEPROM (non-volatile) |
| 동작 온도 범위 | — | -40 °C to +85 °C (industrial) |
| Speed Grade | — | -10 (10 ns tPD) |