EPM5032DI25 vs EPM5032JC Comparación
Comparación detallada lado a lado de EPM5032DI25 por Altera y EPM5032JC por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5032DI25 | EPM5032JC |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $11,10 | $13,50 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | UV-erasable EPLD (CMOS EPROM-based) | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 2 | — |
| Product Terms | 320 | — |
| Output Macrocells | 16 | — |
| Bidirectional I/O Pins | 16 | — |
| Dedicated Inputs | 7 | — |
| Total Inputs | 24 | — |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V |
| I/O Standard | TTL-compatible | — |
| Encapsulado | 24-pin Ceramic DIP (DI) with quartz window | PLCC-44 |
| Programming Technology | UV-EPROM (erasable via quartz window) | — |
| Logic Gates | — | 600 usable gates |
| Maximum I/O Pins | — | 40 |
| Propagation Delay (tPD) | — | [DATA_NEEDED: specific speed grade value] |
| Input Type | — | TTL-compatible |
| Tipo de salida | — | TTL/CMOS-compatible |
| Temperatura de funcionamiento | — | 0C to +70C (commercial) |
| Tipo de montaje | — | Surface Mount (J-lead) |
| Programmability | — | UV-erasable (windowed ceramic) / OTP variants |
| Design Software | — | MAX+PLUS II / Quartus legacy |
| JEDEC Standard | — | JEDEC PLCC-44 footprint |
| Estado RoHS | — | unknown |
| Lead-Free | — | unknown |