EPM5128GC vs EPM5064JC Comparación

Comparación detallada lado a lado de EPM5128GC por Altera y EPM5064JC por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.

Comparación de especificaciones

Parámetro EPM5128GC EPM5064JC
Marca Altera Altera
Categoría FPGA & CPLD FPGA & CPLD
Estado del ciclo de vida Obsolete Obsolete
Estado del stock In Stock In Stock
Precio unitario (USD) $19,20 $7,10
Family MAX 5000 MAX 5000
Macrocells 128 64
Usable Gates 2,500 1,250 (approx.)
Logic Elements / LABs [DATA_NEEDED: LAB count] —
User I/Os 68 —
Package Type WPGA (Windowed Ceramic Pin Grid Array) —
Package Code WPGA —
Number of Terminals 68 —
Terminal Form PIN/PEG (through-hole PGA with alignment pegs) —
Package Shape Square —
Temperature Grade Commercial —
Supply Voltage (Vcc) 5 V —
Process Technology CMOS, UV-erasable —
Architecture EPLD, programmable AND/OR array with fixed OR plane —
Propagation Delay (tpd) [DATA_NEEDED: tpd in ns] —
Maximum Frequency (fmax) [DATA_NEEDED: fmax in MHz] —
Programmable Security Bit Yes —
Configuration Memory Non-volatile UV-EPROM (windowed ceramic) EPROM (UV-erasable window or OTP)
Tipo de montaje Through-Hole (PGA socket required) Surface Mount (socketed)
Estado RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance]
Device Type — EPLD (Erasable PLD)
Logic Array Inputs — 36
Logic Array Outputs — 64
Encapsulado — 68-pin PLCC (JEDEC)
Supply Voltage (VCC) — 5 V (typical, 4.75 V - 5.25 V range)
I/O Logic Level — TTL / CMOS compatible
Temperatura de funcionamiento — [DATA_NEEDED: operating temperature grade]
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) — [DATA_NEEDED: fCNT grade value]
Lead-Free — [DATA_NEEDED: lead-free status]
Nivel MSL — [DATA_NEEDED: MSL rating]
Programming Tool — Altera MAX+PLUS II / Quartus II (legacy device support)

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