EPM5128GC vs EPM5064JC 对比

详细并排对比 EPM5128GC 出自 Altera 和 EPM5064JC 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5128GC EPM5064JC
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $19.20 $7.10
Family MAX 5000 MAX 5000
Macrocells 128 64
Usable Gates 2,500 1,250 (approx.)
Logic Elements / LABs [DATA_NEEDED: LAB count] —
User I/Os 68 —
Package Type WPGA (Windowed Ceramic Pin Grid Array) —
Package Code WPGA —
Number of Terminals 68 —
Terminal Form PIN/PEG (through-hole PGA with alignment pegs) —
Package Shape Square —
Temperature Grade Commercial —
Supply Voltage (Vcc) 5 V —
Process Technology CMOS, UV-erasable —
Architecture EPLD, programmable AND/OR array with fixed OR plane —
Propagation Delay (tpd) [DATA_NEEDED: tpd in ns] —
Maximum Frequency (fmax) [DATA_NEEDED: fmax in MHz] —
Programmable Security Bit Yes —
Configuration Memory Non-volatile UV-EPROM (windowed ceramic) EPROM (UV-erasable window or OTP)
安装类型 Through-Hole (PGA socket required) Surface Mount (socketed)
RoHS 状态 [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance]
Device Type — EPLD (Erasable PLD)
Logic Array Inputs — 36
Logic Array Outputs — 64
封装 — 68-pin PLCC (JEDEC)
Supply Voltage (VCC) — 5 V (typical, 4.75 V - 5.25 V range)
I/O Logic Level — TTL / CMOS compatible
工作温度 — [DATA_NEEDED: operating temperature grade]
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) — [DATA_NEEDED: fCNT grade value]
Lead-Free — [DATA_NEEDED: lead-free status]
MSL 等级 — [DATA_NEEDED: MSL rating]
Programming Tool — Altera MAX+PLUS II / Quartus II (legacy device support)

数据手册与资源

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