EPM5128GI vs EPM5128GC Comparación
Comparación detallada lado a lado de EPM5128GI por Altera y EPM5128GC por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5128GI | EPM5128GC |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $19,85 | $19,20 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Logic Cells / Macrocells | 128 | — |
| Propagation Delay (tPD) | 55 ns | — |
| Tensión de alimentación | 5 V | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Encapsulado | CPGA-68 (Ceramic Pin Grid Array, windowed) | — |
| Recuento de pines | 68 | — |
| Tipo de montaje | Through-hole (socketed PGA) | Through-Hole (PGA socket required) |
| Operating Temperature Grade | Industrial | — |
| Programmability | UV-erasable (windowed), field-programmable | — |
| Configuration Memory | Non-volatile EPROM (no external boot device) | Non-volatile UV-EPROM (windowed ceramic) |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance] |
| Estado del ciclo de vida | Obsolete (last produced by Altera, legacy stock via distributors) | — |
| Macrocells | — | 128 |
| Usable Gates | — | 2,500 |
| Logic Elements / LABs | — | [DATA_NEEDED: LAB count] |
| User I/Os | — | 68 |
| Package Type | — | WPGA (Windowed Ceramic Pin Grid Array) |
| Package Code | — | WPGA |
| Number of Terminals | — | 68 |
| Terminal Form | — | PIN/PEG (through-hole PGA with alignment pegs) |
| Package Shape | — | Square |
| Temperature Grade | — | Commercial |
| Supply Voltage (Vcc) | — | 5 V |
| Process Technology | — | CMOS, UV-erasable |
| Architecture | — | EPLD, programmable AND/OR array with fixed OR plane |
| Propagation Delay (tpd) | — | [DATA_NEEDED: tpd in ns] |
| Maximum Frequency (fmax) | — | [DATA_NEEDED: fmax in MHz] |
| Programmable Security Bit | — | Yes |