EPM5128GI vs EPM5128GC Comparaison
Comparaison détaillée côte à côte de EPM5128GI par Altera et EPM5128GC par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5128GI | EPM5128GC |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $19,85 | $19,20 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Logic Cells / Macrocells | 128 | — |
| Propagation Delay (tPD) | 55 ns | — |
| Tension d'alimentation | 5 V | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Boîtier | CPGA-68 (Ceramic Pin Grid Array, windowed) | — |
| Nombre de broches | 68 | — |
| Type de montage | Through-hole (socketed PGA) | Through-Hole (PGA socket required) |
| Operating Temperature Grade | Industrial | — |
| Programmability | UV-erasable (windowed), field-programmable | — |
| Configuration Memory | Non-volatile EPROM (no external boot device) | Non-volatile UV-EPROM (windowed ceramic) |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance] |
| Statut du cycle de vie | Obsolete (last produced by Altera, legacy stock via distributors) | — |
| Macrocells | — | 128 |
| Usable Gates | — | 2,500 |
| Logic Elements / LABs | — | [DATA_NEEDED: LAB count] |
| User I/Os | — | 68 |
| Package Type | — | WPGA (Windowed Ceramic Pin Grid Array) |
| Package Code | — | WPGA |
| Number of Terminals | — | 68 |
| Terminal Form | — | PIN/PEG (through-hole PGA with alignment pegs) |
| Package Shape | — | Square |
| Temperature Grade | — | Commercial |
| Supply Voltage (Vcc) | — | 5 V |
| Process Technology | — | CMOS, UV-erasable |
| Architecture | — | EPLD, programmable AND/OR array with fixed OR plane |
| Propagation Delay (tpd) | — | [DATA_NEEDED: tpd in ns] |
| Maximum Frequency (fmax) | — | [DATA_NEEDED: fmax in MHz] |
| Programmable Security Bit | — | Yes |