EPM5128GI vs EPM5128JC Comparación
Comparación detallada lado a lado de EPM5128GI por Altera y EPM5128JC por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5128GI | EPM5128JC |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $19,85 | $9,75 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | — |
| Logic Cells / Macrocells | 128 | — |
| Propagation Delay (tPD) | 55 ns | 35 ns |
| Tensión de alimentación | 5 V | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Encapsulado | CPGA-68 (Ceramic Pin Grid Array, windowed) | — |
| Recuento de pines | 68 | — |
| Tipo de montaje | Through-hole (socketed PGA) | Surface Mount (PLCC socket or solder) |
| Operating Temperature Grade | Industrial | — |
| Programmability | UV-erasable (windowed), field-programmable | — |
| Configuration Memory | Non-volatile EPROM (no external boot device) | UV-erasable EPROM (windowed package) |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status - legacy part] |
| Estado del ciclo de vida | Obsolete (last produced by Altera, legacy stock via distributors) | — |
| Product Family | — | MAX 5000 |
| Device Type | — | EPLD / CPLD |
| Macrocell Count | — | 128 |
| Logic Elements | — | Programmable AND/OR/XOR array |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Número de pines | — | 68 |
| Package Type | — | PLCC-68 (JLCC) ceramic, J-leaded |
| Dedicated Inputs | — | 8 |
| User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Programming Interface | — | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Temperatura de funcionamiento | — | Commercial 0C to +70C |
| Boundary Scan | — | JTAG IEEE 1149.1 (family feature) |
| Process Technology | — | CMOS EPROM |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |