EPM5128GI vs EPM5128JC Comparaison
Comparaison détaillée côte à côte de EPM5128GI par Altera et EPM5128JC par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5128GI | EPM5128JC |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $19,85 | $9,75 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | — |
| Logic Cells / Macrocells | 128 | — |
| Propagation Delay (tPD) | 55 ns | 35 ns |
| Tension d'alimentation | 5 V | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Boîtier | CPGA-68 (Ceramic Pin Grid Array, windowed) | — |
| Nombre de broches | 68 | — |
| Type de montage | Through-hole (socketed PGA) | Surface Mount (PLCC socket or solder) |
| Operating Temperature Grade | Industrial | — |
| Programmability | UV-erasable (windowed), field-programmable | — |
| Configuration Memory | Non-volatile EPROM (no external boot device) | UV-erasable EPROM (windowed package) |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status - legacy part] |
| Statut du cycle de vie | Obsolete (last produced by Altera, legacy stock via distributors) | — |
| Product Family | — | MAX 5000 |
| Device Type | — | EPLD / CPLD |
| Macrocell Count | — | 128 |
| Logic Elements | — | Programmable AND/OR/XOR array |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Nombre de broches | — | 68 |
| Package Type | — | PLCC-68 (JLCC) ceramic, J-leaded |
| Dedicated Inputs | — | 8 |
| User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Programming Interface | — | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Température de fonctionnement | — | Commercial 0C to +70C |
| Boundary Scan | — | JTAG IEEE 1149.1 (family feature) |
| Process Technology | — | CMOS EPROM |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |