EPM5128LC2 vs EPM5128LC-1 Comparación
Comparación detallada lado a lado de EPM5128LC2 por Altera y EPM5128LC-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5128LC2 | EPM5128LC-1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $22,40 | $8,20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 8 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Global Clock Inputs | 1 dedicated | — |
| Propagation Delay (tPD) | 45 ns | — |
| Supply Voltage (VCC) | 5 V | 5 V (±10%) |
| Process Technology | CMOS EPROM | CMOS EPROM, UV-erasable |
| Configuration Memory | On-chip EPROM (non-volatile) | — |
| Boundary Scan | JTAG / IEEE 1149.1 | — |
| Temperatura de funcionamiento | -40 C to +85 C (extended commercial) | 0C to +70C (commercial) |
| Encapsulado | PGA (Pin Grid Array, ceramic) | — |
| Tipo de montaje | Through-Hole / Socketed | Surface Mount (J-lead PLCC socket compatible) |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Logic Elements / Macrocells | — | 128 macrocells |
| Number of Usable Gates | — | [DATA_NEEDED: usable gates] |
| Dedicated Inputs | — | 7 |
| Bidirectional I/O Pins | — | 52 |
| Total User I/O | — | 60 (max) |
| Propagation Delay (tpd) | — | 30 ns |
| Programmability | — | UV-erasable / OTP (windowed package) |
| Package Type | — | 68-pin J-lead ceramic chip carrier (PLCC windowed) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |