EPM5130JC-1 vs EPM5130WC-2 Comparación
Comparación detallada lado a lado de EPM5130JC-1 por Altera y EPM5130WC-2 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5130JC-1 | EPM5130WC-2 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,25 | $62,00 |
| Product Type | CPLD (Complex Programmable Logic Device) | UV-Erasable PLD (CPLD) |
| Family | MAX 5000 | — |
| Usable Gates | 2,500 gates | — |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 8 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tPD) | 40 ns | 45 ns |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Dedicated Inputs | 19 | 19 |
| I/O Pins | 80 | — |
| Encapsulado | 84-pin PLCC (J-lead) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Programming Technology | UV-erasable EPROM (quartz window) | — |
| Process Technology | CMOS | CMOS |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0 °C to 70 °C (Commercial) |
| External Clock Pins | 1 global clock | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 5000 |
| Macrocell Count | — | 128 |
| User I/O Lines | — | 48 |
| Total Inputs (I/O + dedicated) | — | 68 |
| Package Type | — | 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing |
| Terminal Pitch | — | 0.650 mm |
| Configuration Memory | — | UV-erasable CMOS EEPROM cells |
| Speed Grade | — | -2 (45 ns) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Logic Elements | — | AND/OR array with programmable macrocell register |