EPM5130JI vs EPM5130JC-1 Comparación
Comparación detallada lado a lado de EPM5130JI por Altera y EPM5130JC-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5130JI | EPM5130JC-1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,75 | $9,25 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable EPLD (CMOS EPROM) | — |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| Frecuencia de reloj máxima | 33.3 MHz | — |
| Propagation Delay (tPD) | 55 ns | 40 ns |
| External Clock Inputs | 1 (shared input/clock) | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Process Technology | 0.75 micron CMOS EPROM | CMOS |
| Tensión de alimentación | 5 V (typical) | — |
| Input Logic Standard | TTL-compatible | — |
| Package Type | Ceramic J-Leaded Chip Carrier (JLCC) with UV window | — |
| Temperatura de funcionamiento | Commercial (0C to +70C) | 0C to +70C (commercial) |
| Program/Erase Method | UV erasure through quartz window | — |
| Estado RoHS | Non-compliant (contains Pb in ceramic package) | [DATA_NEEDED: RoHS compliance] |
| Lifecycle | Obsolete - EOL by Altera/Intel | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 2,500 gates |
| Maximum Operating Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Dedicated Inputs | — | 19 |
| I/O Pins | — | 80 |
| Encapsulado | — | 84-pin PLCC (J-lead) |
| Tipo de montaje | — | Surface Mount |
| Programming Technology | — | UV-erasable EPROM (quartz window) |
| External Clock Pins | — | 1 global clock |