EPM5130QC-1 vs EPM5130JC-1 Comparación
Comparación detallada lado a lado de EPM5130QC-1 por Altera y EPM5130JC-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5130QC-1 | EPM5130JC-1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $9,25 |
| Family | MAX 5000 | MAX 5000 |
| Product Type | UV-Erasable / OTP Complex PLD (CPLD) | CPLD (Complex Programmable Logic Device) |
| Logic Cells / Macrocells | 128 macrocells | — |
| Usable Gates (marketing) | 5130 gates | — |
| Speed Grade | -1 | — |
| Encapsulado | PQFP-100 (windowed ceramic) | 84-pin PLCC (J-lead) |
| Terminal Pitch | 0.635 mm | — |
| Process Technology | CMOS | CMOS |
| Configuration Memory | UV-Erasable EPROM | — |
| Tensión de alimentación | 5 V (single) | — |
| Temperatura de funcionamiento | Commercial (0 C to +70 C) | 0C to +70C (commercial) |
| Programmable Polarity | Yes (per macrocell) | — |
| Boundary Scan / JTAG | Per MAX 5000 family | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance] |
| Usable Gates | — | 2,500 gates |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Propagation Delay (tPD) | — | 40 ns |
| Supply Voltage (VCC) | — | 5 V |
| Dedicated Inputs | — | 19 |
| I/O Pins | — | 80 |
| Programming Technology | — | UV-erasable EPROM (quartz window) |
| External Clock Pins | — | 1 global clock |