EPM5192AGC-15 vs EPM5192AGC84-15 Comparación
Comparación detallada lado a lado de EPM5192AGC-15 por Altera y EPM5192AGC84-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192AGC-15 | EPM5192AGC84-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $27,80 | $42,00 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | MAX 5000 | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (typical for 192-macrocell MAX 5000) | — |
| Maximum User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | 15 ns |
| Supply Voltage (VCC) | 5 V | 4.5 V to 5.5 V |
| Technology | CMOS, UV-erasable EPROM | — |
| Encapsulado | Ceramic Pin Grid Array (PGA) | 84-pin Ceramic PGA (Pin Grid Array) |
| Programming Method | UV erase + EPROM program (via Altera programmer) | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) - [DATA_NEEDED: military/industrial temp grade range] |
| Estado RoHS | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] | [DATA_NEEDED: not declared in web data; ceramic PGA with UV window typically non-RoHS] |
| Estado del ciclo de vida | Obsolete / Last Time Buy (per Altera legacy product list) | — |
| Family | — | MAX 5000 |
| Device Type | — | UV-Erasable/OTP Complex PLD |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Maximum Internal Clock Frequency | — | 83.3 MHz |
| Process Technology | — | CMOS |
| Programmable Element | — | UV-Erasable EPROM cell |
| Tipo de montaje | — | Through-Hole |