EPM5192AGC-15 vs EPM5192AGC84-15 Comparaison
Comparaison détaillée côte à côte de EPM5192AGC-15 par Altera et EPM5192AGC84-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192AGC-15 | EPM5192AGC84-15 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $27,80 | $42,00 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | MAX 5000 | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (typical for 192-macrocell MAX 5000) | — |
| Maximum User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | 15 ns |
| Supply Voltage (VCC) | 5 V | 4.5 V to 5.5 V |
| Technology | CMOS, UV-erasable EPROM | — |
| Boîtier | Ceramic Pin Grid Array (PGA) | 84-pin Ceramic PGA (Pin Grid Array) |
| Programming Method | UV erase + EPROM program (via Altera programmer) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) - [DATA_NEEDED: military/industrial temp grade range] |
| Statut RoHS | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] | [DATA_NEEDED: not declared in web data; ceramic PGA with UV window typically non-RoHS] |
| Statut du cycle de vie | Obsolete / Last Time Buy (per Altera legacy product list) | — |
| Family | — | MAX 5000 |
| Device Type | — | UV-Erasable/OTP Complex PLD |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Maximum Internal Clock Frequency | — | 83.3 MHz |
| Process Technology | — | CMOS |
| Programmable Element | — | UV-Erasable EPROM cell |
| Type de montage | — | Through-Hole |