EPM5192AGC vs EPM5192GC84-1 Comparación
Comparación detallada lado a lado de EPM5192AGC por Altera y EPM5192GC84-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192AGC | EPM5192GC84-1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $56,00 | $14,20 |
| Family | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) | MAX 5000 |
| Device Type | UV-Erasable / OTP Complex PLD (EPLD) | — |
| Macrocells | 192 | 192 |
| Logic Density | High-density (per MAX 5000 family definition) | — |
| Architecture | CMOS, sum-of-products with macrocell output logic | Shared input/clock and shared product terms |
| Process Technology | CMOS | — |
| Encapsulado | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) | 84-pin PGA (Pin Grid Array), WPGA code |
| Speed Grade Suffix | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | — |
| Programmability | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) | — |
| Security Bit | Programmable security bit (per MAX 5000 family) | — |
| Tensión de alimentación | [DATA_NEEDED: VCC nominal and tolerance] | — |
| Tipo de montaje | Through-hole (Pin Grid Array) | Through-hole (PGA socket) |
| Estado RoHS | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) | Compliant (per third-party distributor listing) |
| Lifecycle | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) | — |
| Programming Support | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers | — |
| Product Type | — | UV-Erasable/OTP Complex PLD (CPLD) |
| Technology | — | CMOS (EPROM-cell based) |
| Propagation Delay (tPD) | — | 40 ns (speed grade -1) |
| Frecuencia de reloj máxima | — | 50 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Dedicated Inputs | — | 7 |
| User I/O Pins | — | 64 |
| Total Inputs / Outputs | — | 72 inputs / 64 outputs |
| Temperature Grade | — | Commercial |
| Programming Method | — | UV erasure (quartz window) + EPROM programmer |
| Logic Element Type | — | Macrocells with AND/OR array |